2025-09-02 –, Bonjour 50
Tracing FPGAs in heterogeneous systems remains a significant challenge. Vendor-provided hardware tracing tools often have limited trace durations, which restrict visibility into complex and long-running issues. When combined with the inherent complexity of heterogeneous platforms, this limitation makes debugging and performance analysis especially difficult. Tracing software and hardware separately further complicates matters, as aligning software events with FPGA logic becomes a tedious and error-prone task, leaving designers without a clear understanding of system-wide behaviors. This presentation introduces a solution that bridges this gap: a combined tracing approach that integrates FPGA and software event traces into a unified view. Our work comprises an FPGA core capable of tracing AXI transactions, signals, and state machines, along with a software component that collects and processes the trace data. The FPGA core timestamps events and transmits them over DMA to software, where they are stored with synchronized time markers for post-processing. The result is a cohesive, time-aligned trace that can be analyzed in conjunction with software traces, offering designers deeper insight into system interactions and making root cause analysis more accessible.
Tarek Ould-Bachir received his M.A.Sc. and Ph.D. degrees in Electrical Engineering from Polytechnique Montréal, Montréal, QC, Canada, in 2008 and 2013, respectively. He is currently an Associate Professor in the Department of Computer and Software Engineering at Polytechnique Montréal, where he also serves as Graduate Programs Coordinator.
His research focuses on designing programmable architectures for high-performance embedded systems, with applications in real-time simulation, FPGA-based acceleration, and high-speed packet processing. He has made significant contributions to electromagnetic transient (EMT) simulation, power electronics modeling, and hardware-in-the-loop (HIL) platforms. His recent work also addresses the cybersecurity of transportation systems, including autonomous vehicles and avionics platforms, where real-time constraints and system resilience are critical. In parallel, he is exploring unconventional computing paradigms, such as stochastic computing and Ising machines, to tackle complex combinatorial optimization problems in hardware.
Dr. Ould-Bachir has authored or co-authored more than fifty peer-reviewed publications in leading journals and conferences. He is actively involved in the IEEE Industrial Electronics Society (IES), where he currently serves as Chair of the Technical Committee on Electronic Systems on Chip (ESoC) for the 2023–2025 term. He regularly contributes to the organization of international workshops and conferences related to FPGA systems, embedded architectures, and cyber-physical simulation technologies. He is a licensed member of the Ordre des ingénieurs du Québec (OIQ) and a member of the IEEE, the Association for Computing Machinery (ACM), and the Regroupement Stratégique en Microsystèmes du Québec (ReSMiQ), a provincial strategic cluster supporting innovation in microsystems. He is also a member of the Multidisciplinary Institute for Cybersecurity and Cyber Resilience (IMC²), an initiative hosted at Polytechnique Montréal that brings together academic, industrial, and governmental partners to advance cybersecurity. Additionally, he serves as co-director of the Microelectronics and Microsystems Research Group (GRM), which specializes in the design and validation of high-performance and secure integrated systems.
François Tétreault is a Base Solution Architect at Ciena with over 30 years of industrial R&D experience, including 11 years of collaboration on research projects with universities. His expertise lies in operating systems, embedded systems, and low-level debugging tools, particularly in observability and software tracing. His recent work extends software tracing techniques to FPGAs and digital logic devices.